1. Field of the Invention
The present invention relates generally to samplers that sample an input signal Sin and hold a corresponding output voltage Vout through successive and alternate sampling and holding time periods.
2. Description of the Related Art
Signal samplers are typically used to successively sample and hold the amplitudes of analog signals and provide the resulting samples for further processing (e.g., in an analog-to-digital conversion). Sampler structures have been described under various names (e.g., sample and holds, sample-and-hold amplifiers (SHAs) and track and hold circuits) and various structural configurations have been proposed (e.g., see U.S. Pat. Nos. 4,962,325 issued Oct. 9, 1990 to Miller, et al., 5,315,170 issued May 25, 1994 to Vinn, et al., 5,389,929 issued Feb. 14, 1995 to Nayebi, et al., 5,418,408 issued May 23, 1995 to Mangelsdorf, et al., 5,457,418 issued Oct. 10, 1995 to Chang, 5,838,175 issued Nov. 17, 1998 to Hsieh and 6,028,459 issued Feb. 22, 2000 to Birdsall, et al.).
Although various conventional sampler configurations can sample and hold an input signal Sin, their structures often corrupt this process so that the correlation between the input signal Sin and a corresponding output voltage Vout is degraded. FIG. 3 of U.S. Pat. No. 4,962,325, for example, shows a switched-capacitor prior art sampler in which serially-arranged input switches gate an input signal to sampling capacitors that are coupled to the input of a differential output amplifier. Other switches facilitate transfer of charges from the sampling capacitors to output capacitors that are arranged across the differential output amplifier.
When the serially-arranged input switches are realized with high speed transistors, the input signal Sin is typically passed through the transistors"" current terminals and this passage is gated with control signals on the transistors"" control terminals. In this arrangement, however, the input switches corrupt the input signal Sin with consequent degradation (e.g., harmonic distortion) of the sampler""s output voltage Vout.
The present invention is directed to sampler methods and structures that enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. These goals are realized by providing a supply current to an input buffer to enable it during sampling time periods and removing the supply current to disable and isolate the input buffer during holding time periods.
In the sampling time periods, the bottom plate of a sampling capacitor Cs is directly charged through the input buffer to a charge that corresponds to the input signal Sin.
In the holding time periods, the input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled the capacitor""s bottom plate to transfer electrical charge from the sampling capacitor Cs to the output capacitor Co and thereby generate the output voltage Vout across the output capacitor Co.
These processes facilitate the replacement of serially-arranged switches and their attendant harmonic distortion with an alternately enabled and disabled input buffer that alternately charges a sampling capacitor Cs and is isolated from the sampling capacitor Cs. Sampler embodiments are described for practicing the processes of the invention.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.